1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a drive circuit of an FRAM for generating a drive signal for performing an operation despite address noise.
2. Discussion of Related Art
Ferroelectric thin films have been developed for as a dielectric film of a capacitor. The ferroelectric thin films improve a refresh operation of DRAM (Dynamic Random Access Memory) devices with large capacities. A ferroelectric random access memory (FRAM, FeRAM) using such a ferroelectric thin film is a nonvolatile memory device having high-speed access, low power consumption and durable construction. FRAM may be implemented in various kinds of electronic equipment having file storage and search functions, such as portable computers, cellular phones, game machines, etc. FRAM may be implemented in other applications, including for example, as a record medium for recording sounds or images.
In FRAM, a memory cell comprises a ferroelectric capacitor and an access transistor. The memory cell stores a logic data state, e.g., ‘1’ or ‘0’, through an electric polarization state of the ferroelectric capacitor. When voltage is applied to both ends of the ferroelectric capacitor, a ferroelectric material of the ferroelectric capacitor is polarized. A polarization state of the ferroelectric material corresponds to a direction of an electric field produced by the voltage. A switching threshold voltage for controlling the polarization state of the ferroelectric material is a coercive voltage. To read data stored in the memory cell, a voltage is applied to generate a potential difference between both electrodes of the ferroelectric capacitor, and the logic data state stored in the memory cell is sensed by a change of charge in a coupled a bit line.
FIG. 1 illustrates a hysteresis curve of the ferroelectric material of the ferroelectric capacitor.
Referring to FIG. 1, when a ground voltage Vss or 0V is applied to the capacitor no electric field is applied to the ferroelectric material and polarization is not generated. When a voltage applied to both ends of the ferroelectric capacitor increases in a positive direction, a polarization level or charge amount increases to a state point A of a positive polarization region from zero. At the state point A, polarization occurs in one direction, and a polarization level at the state point A has a high value. The high polarization level, namely, the charge amount that the ferroelectric material retains, is represented as +Qs. Even though the voltage of both ends of the capacitor falls to ground voltage Vss, a polarization level does not fall to zero but remains at a state point B. The charge amount that ferroelectric material retains is a residual polarization level represented as +Qr. When the voltage of both ends of the capacitor increases in a negative direction, the polarization level is changed to a state point C of a negative charge polarization region from the state point B. At the state point C, the ferroelectric material is polarized in a direction opposite to the polarization direction of the state point A. The polarization level at state point C is represented as −Qs. Even though the voltage of both ends of the capacitor falls to a ground voltage Vss, the polarization level does not fall to zero but remains at a state point D. The residual polarization level at the state point D is represented as −Qr. When the voltage applied to both ends of the capacitor again increases in the positive direction, the polarization level of the ferroelectric material is changed to the state point A from the state point D.
FIG. 2 illustrates a memory cell of a memory cell array in an FRAM.
With reference to FIG. 2, a memory cell is constructed of one access transistor M1 and one ferroelectric capacitor CFE. The access transistor M1 has two terminals, a source terminal and a drain terminal, which are respectively connected between one terminal of the ferroelectric capacitor CFE and a bit line B/L. A gate of the access transistor M1 is connected to a word line W/L. A first terminal of the ferroelectric capacitor CFE is coupled to the access transistor M1, and a second terminal thereof is coupled to a plate line P/L.
When a voltage sufficient to generate an electric field is applied to the ferroelectric capacitor, formed of the ferroelectric material disposed between the terminals, a polarization direction set based on a spontaneous polarization is maintained. A surface charge of the ferroelectric material through the spontaneous polarization is not lost naturally by leakage, etc. If a voltage is not applied in an opposite direction so that the polarization level becomes zero, the polarization direction is maintained.
When a voltage is applied in the positive direction to the ferroelectric capacitor and then removed, the residual polarization of the ferroelectric material constituting the ferroelectric capacitor becomes +Qr. When a voltage is applied in the negative direction to the ferroelectric capacitor and then removed, the residual polarization of the ferroelectric material becomes −Qr. When the residual polarization has a state of +Qr, namely, at the state point B, a logic state indicates data ‘0’. When residual polarization has a state of −Qr, namely, at the state point D, a logic state indicates data ‘1’. A charge difference in changing from the state point A to the state point B is a voltage corresponding to the amount of non-switching capacitance Qnsw. The non-switching capacitance Qnsw is distinguished from a charge difference in changing from the state point D to the state point A, namely, a voltage corresponding to a switching capacitance Qsw. The switching capacitance Qsw corresponds to a read operation on data stored in memory cell.
An asynchronous FRAM operates according to an external chip control signal, e.g., an external enable signal or external chip selector signal. When the external chip control signal is enabled, an applied external address transition is detected to control a cycle operation by using a composite pulse signal obtained by totaling respective address transition detection signals. An internal clock is generated by the composite pulse signal, and through the composite pulse signal, read and write operations for a corresponding address of memory can be performed. When an external address is changed, a composite pulse signal is generated, and a precedent cycle operation is completed by this signal and a next cycle preparation operation proceeds. Further, an internal chip enable signal (ICE) is generated by the composite pulse signal, and the internal control signals needed for operation of a memory device are generated by the internal chip enable signal. Thus, a time for generation of the composite pulse signal is important to an operation of the memory device.
FIG. 3 illustrates timings for a read operation in an FRAM.
As shown in FIG. 3, a read operation in an FRAM starts by a transition and enabling of an external chip control signal XCEB from a logic ‘high’ level to a logic ‘low’ level.
An external address signal XA is applied by the enabling of the external chip control signal XCEB. The external address XA is applied to an address buffer circuit (not shown). The address buffer circuit buffers the applied external address signal XA and generates an internal address signal. Further, the address buffer circuit detects a transition of the internal address signal and generates address transition detection signals for respective address signals. The address transition detection signals are totaled in a composite pulse signal generating circuit, and become a composite pulse signal ATD_SUM as an address transition detection signal. The composite pulse signal ATD_SUM is a short pulse signal that is enabled for a given time and then disabled.
An internal chip enable signal ICE is generated by the composite pulse signal ATD_SUM, and the internal control signals needed for operation of a memory device are generated by the internal chip enable signal ICE. The internal chip enable signal is not generated in a transition for enabling the composite pulse signal ATD_SUM, but is generated in a transition for disabling the composite pulse signal ATD_SUM after the address transition detection signals are applied.
When the internal chip enable signal ICE is generated, a word line W/L is enabled by a word line decoder and driver circuit (not shown). A plate line P/L is enabled by a plate control signal generated in response to the internal chip enable signal ICE.
When the plate line P/L is enabled, operation at a charge sharing interval t1 starts. A voltage corresponding to data stored in a memory cell is developed to a bit line B/L, that maintains a ground level state at the charge sharing interval t1.
A sense amplifier enable signal SAEN, responding to an enabling of the plate control signal, is generated, enabling a sense amplifier. When the sense amplifier is enabled, operation at the charge sharing interval t1 is finished, and operation of a sensing interval t2 starts. At the sensing interval t2, data developed to the bit lint B/L is sensed and amplified by the sense amplifier.
The operation at the sensing interval t2 is finished by a disabling of the plate line P/L through the plate control signal, and operation of a write-back interval t3 starts.
At the write-back interval t3, previous data is restored; data stored in a memory cell is reversed when a plate line is enabled for a general read operation and needs to be restored. The write-back interval t3 needs to be sufficient to prevent a breakage of data stored in a memory cell.
The operation of the write-back interval t3 continues until the sense amplifier is disabled by a subsequently generated composite pulse signal ATD_SUM after disabling the plate line P/L.
When the sense amplifier is disabled, the internal chip enable signal and the word line W/L are disabled, and the read operation is completed. In a transition for disabling the subsequently generated composite pulse signal ATD_SUM, an internal chip enable signal is again generated, and the next operation is performed.
FIG. 4 illustrates timings for an abnormal operation, e.g., a read operation including address noise, in an FRAM.
As shown in FIG. 4, in a read operation is performed until the sensing interval t2, similar to FIG. 3. To perform a restoring operation when the sensing interval t2 is finished and an operation of the write-back interval t3 starts, sufficient time is needed. In a case where noise occurs in an address signal, the composite pulse signal ATD_SUM to be subsequently generated is generated early and a time to perform the restoring operation is shortened. The read operation is finished under such a state that sufficient time to perform restoring operation is not provided. Thus, breakage of data stored in memory cells may be caused.
Therefore, a need exists for a drive circuit of an FRAM for generating a drive signal for performing an operation despite address noise.